Chip-level and multi-node analysis of energy-optimized lattice-Boltzmann CFD simulations

摘要

Memory-bound algorithms show complex performance and energy consumptionbehavior on multicore processors. We choose the lattice-Boltzmann method (LBM)on an Intel Sandy Bridge cluster as a prototype scenario to investigate if andhow single-chip performance and power characteristics can be generalized to thehighly parallel case. First we perform an analysis of a sparse-lattice LBMimplementation for complex geometries. Using a single-core performance model,we predict the intra-chip saturation characteristics and the optimal operatingpoint in terms of energy to solution as a function of implementation details,clock frequency, vectorization, and number of active cores per chip. We showthat high single-core performance and a correct choice of the number of activecores per chip are the essential optimizations for lowest energy to solution atminimal performance degradation. Then we extrapolate to the MPI-parallel leveland quantify the energy-saving potential of various optimizations and executionmodes, where we find these guidelines to be even more important, especiallywhen communication overhead is non-negligible. In our setup we could achieveenergy savings of 35% in this case, compared to a naive approach. We alsodemonstrate that a simple non-reflective reduction of the clock speed leavesmost of the energy saving potential unused.